Overview

Recently I was interviewed with a design question regarding coherence. The problem statement is like this. We have a server that hold the ground truth of the data (like a database or key-value store). We also have many clients that may read the data from the sever and make local updates to the data. What kind of design guidence should we consider for such system. This is acutally a similiar problem as cache coherence for multi-core system. In this blog I will reveiw the classic MESI protocol for cache coherence.

I have been noticing that lots of huge C/C++ projects use Google testing framework (i.e. GTest). However, in the past I thought this is not worth integrating third-party testing framework in my medium/small projects. I am used to writing my own test case for unit tests which is simple and flexible to change according to my needs and more importantly doesn’t need any dependant packages. Recently, I found most platforms already has Gtest installed and integrating Gtest to my own project can actually accelerate unit test process with a lot of advanced features (like repeat test and break on failure) provided by Gtest. This blog summarizes the basic elements of Gtest, usage and provide some useful resources.

This blog summarizes some tricks when writing bash script.

This blog briefly talks about the GNU build toochain, (i.e. autoconf, automake) and how to use it. As a long time Linux user. Probably we all know the below build process for something that cannot retrieve binary directly from package manager but needs to be compiled from source.

An interesting interview question for architecture positions is how to measure the instruction window size. To answer this question, you need to have a full understanding of the modern OOO microarchitecture. Instruction window refers to the maximum number of instructions which can execute out-of-order in a processor. It is bounded by the reorder buffer (ROB) size. The reorder buffer is used for in-order instruction commit to implement precise exception. In the pipeline, during assigning entry to the reservation station, an entry in reorder buffer will be allocated and the destination register will be renamed with the reservation station entry tag (basically a reservation station entry ID). Once the instruction is executed, it will broadcast to ROB and reservation station to notify the finish of the instruction and data dependancy. The ROB will be constantly checked and deallocated in-order to commit the instructions in-order.